Welcome
On this website the properties of RS flip-flops comprehensive, understandable and - this is particularly important -
correctly describes.
Since 1982 I have been trying to convince the professional world to finally present the properties of an RS flip-flop comprehensively and correctly.
In 1984 with a patent, in 2004 with an article in a trade journal and since 2008 on the Internet. Unfortunately, this has only led to success
for a few by 2021. It is easier to stick with wrong things you are used to than to bother trying to grasp something new.
In both German and English Wikipedia, my posts there were deleted in 2009 by overburdened responsible persons.
My comprehensive/correct description of the properties of an RS flip-flop leads to new applications. For example,
to "Ideal pulse circuits" or to "Asynchronous (non-clocked) JK flip-flops", as described on the following pages.
On the next page (RS flip-flop) a few bad or wrong examples - as they are common in literature and on the Internet - are shown, in order to
then recognize how it is correct.
Especially in forums I noticed how incompetent "experts" gave their advice - terrible.
Why am I thinking of a quote from Albert Einstein at this point?
"Two things are infinite: the universe and human stupidity;
and I'm not sure about the universe" (Albert Einstein)
Briefly about the history of the RS flip-flop:
When the two Englishmen Eccles and Jordan invented the FipFlop circuit, they ultimately wanted to save information (1-bit for counting circuits).
For such an application it was only important to be able to set and reset a bit. Therefore, the possibility of applying a set and a reset signal
at the same time was ignored for understandable reasons.
This input assignment (R = S = 1 for NOR gates) is an important part of the complete description of the properties of an RS flip-flop, because it
can be used in an extended application of the RS flip-flop, for example to create an "ideal pulse circuit" and a "asynchronous
JK flip-flop "1), as it was developed by me in 1982.
Here my view, also proven with these circuits, differs fundamentally from those who represent the (wrong) "doctrine".
This is what the ALTERNATIVE stands for on my website.
The Wikipedia from different countries treat the input assignment (R = S = 1 for NOR gates) sometimes differently from each other.
Sometimes this case is simply ignored out of uncertainty. There have always a little been changes in the past few years.
Here is my very simple Python program for the n-dimensional Fibonacci search!
But in one thing all of them have been always stayed true to: the statements on this special case remained inadequate or incorrect.
Sometimes one had to doubt the author's technical expertise. This also applied to so-called seesaw examples for explanation how the RS flip-flop
works, for example in the German Wikipedia.
To date, I haven't found a really clear and understandable animation of an RS flip-flop on the Internet.
That's why I created the RS flip-flop animation on the next page (RS flip-flop) myself
I often get the impression that the writers have passed the highest level of incompetence and don't care what nonsense they write.
My new circuits are not easy to understand, even for real experts. It is actually the case that the
"Disregarded" input assignment R = S = 1 occurs again and again, but a faulty / indeterminate situation never occurs, because never after that
R = S = 0 follows or can follow. There are no so-called "race conditions".
When I developed (1982) the circuits shown on the following pages, the only technical aids I had, were paper and pencil.
Mr. Dumler has now carried out a detailed analysis of these circuits using modern technical means and documented them in an analysis report. The result proves my beliefs. Everyone who is interested but also doubts should read it.
Conclusions
The statements on this website are intended to show that the usual definition or description of the RS flip-flop needs to be revised. It is shown how the input assignment R = S = 1 (NOR) can be used sensibly. As a result, ideal pulse circuits can be realized without an RC combination, whereby, for example, non-clocked (asynchronous) JK flip-flops can be implemented. There are also simple options for building monolithic circuits, for example. The circuits shown are advantageous wherever the highest possible cut-off frequency has to be achieved or where no clock signal is available.
1) Note:
The circuits were first published on May 9th, 1984 under the economic patent WP H 03 K / 2432 692 (now deleted)
Developer of the circuits: Homepage owner Klaus-Eckart Schulz
Copyright-Note
The circuits may be reproduced, however, the reference to the developer is required.