## RS flip-flop

The most simple flip-flop is the RS flip-flop. Its circuit is shown in fig. 1. On this site it is assumed that the RS flip-flop with NOR gates is set up (see figure 1). This is not a limitation. When using NAND gates only need the appropriate transformation rules to be observed.
If S (Set) is pulsed high while R (Reset) is held low (S=1,R=0), the output Q1 is forced high (1)) and Q2 is forced low (0)) (Q1=1,Q2=0).With the subsequent change to S=R=0, the outputs will not changed. That means this state is stored.

But what happens if both inputs receive a 1-signal (S=R=1)?
In books and the internet are found in the description of RS flip-flops and the associated characteristic tables statements such as:
- "R=S=1 is forbidden or strictly to be avoided or nonsense"
- "R=S=1 is unstable or metastable"
- "R=S=1 leads to an unstable state"
- "R=S=1 leads to no change of state"
.
We will critical confront us with these views in the following.
Fig. 1 RS Flip-flop

## A simulation/animation of a RS flip-flop in Transistor-Transistor-Logic

This animation shows the correct operation of the RS flip-flop and is very easy to understand.
The input assignments can be varied as desired by clicking on the buttons. Important currents are shown.
However, a good and complete animation requires a browser that fully supports scalable vector graphics.
Very suitable are Firefox, Chrome, Safari.

 Signal R, S Q1, Q2 0 ≤0,8V ≤0,4V 1 ≥2,0V ≥2,4V

### The main forms of description in the literature and the Internet

0. Basics
If it is generally spoken of a RS flip-flop, it refers to the hardware implementation the flip-flop by means of two back-coupled NOR or NAND gates. This is the basis for all statements on this circuit together with the corresponding truth table!
A truth table shows the static end state of a system at a defined input assignment. To show transition states graphs are used.

1. The input assignment S=R=1 is forbidden or strictly avoided.

 S R Q /Q Remark 0 0 Qn /Qn Save the state 1 0 1 0 Set 0 1 0 1 Reset 1 1 - - Forbidden

It is expected that the RS flip-flop should only serve as a memory. This means that the states for all possible inputs should be able to be stored. The storage is done with R=S=0. Saving the current state is only possible with the transition from R not equal S (R=1 and S=0 or R=0 and S=1) to R=S=0. Was previously R=S=1 (that means (Q1=Q2=0) then it is not sure in which state the flip flop will tilt. So is R=S=1 summarily banned. In many cases certainly a reasonable restriction. The characteristic table in which R=S=1 is marked as forbidden, is not really a characteristic table that reflects the nature of the two feedback gates. It is a restricted table that defines how the user the function of the RS flip-flop wishes (Definition table). The restriction is not caused by the circuit, but a restriction by the author. This representation is relativly good to understand. Then for the present there is no reason to know why R=S=1 should be usefull. That is a mistake. We will see, despite the ban R=S=1 can be very usefull.
Since in this case Q1 and Q2 are always inversely to each other, standing in the characteristic table Q for Q1 and /Q instead of Q2.

2. The input assignment S=R=1 is unstable / metastable

 S R Q1 Q2 Remark 0 0 Q1n Q2n Save the state 1 0 1 0 Set 0 1 0 1 Reset 1 1 0 0 Unstable/metastable(Race Condition)

Apparently the same idea as in the first case that each input assignment must be saved. However, the input assignment R=S=1 is not banned in general. It will be assigned clearly in the character-istic table for both outputs 0. Correctly for a holistic view of the circuit. In the further descriptions but this condition will described as unstable / metastable, in apparent contradiction to their own characteristic table and into reality. On the contrary, this condition is also very stable. As long as R=S=1 remains, it will change nothing.
Also in this case, the author thinks, however, again one step further towards saving the state, which is of course not possible. This instability can occur only if R=S=0 follows, has nothing to do with R=S=1 in the characteristic table!!
A representative of this view was at the time of publishing this website, the German Wikipedia (see home-page paragraph 1.)

3. The input assignment S=R=1 follows an unstable / metastable state.

From the foregoing it is clear that this statement is only true if S=R=0 follows, because this state can not be stored.
In the English Wikipedia was e.g. assumed to October 2010 in the truth table shown assumes that the state with the appearance of the input assignment R=S=1 does not change (see home-page paragraph 1.) This means that input allocation was ignored.

### Conclusions

One is all previous (see home-page paragraph 1.) representations common:
The truth tables and descriptions are models that claim for the case R=S=1 (NOR gates), as this case is to be treated, regardless of actual conditions at the actual object.
That must lead to contradictions, since the reality does not depend on the models.

Even the use of simulation programs, caution when using ready RS-FF-units. I tested second. Both did not respond to an R=S=1 input assignment. In such cases it is safer to build such a module itself by 2 NOR- or NAND-gates.

What should be done?

 S R Q1 Q2 Remark 0 0 Q1n Q2n Save the state 1 0 1 0 Set 0 1 0 1 Reset 1 1 0 0 Race Condition

It would be desirable and appropriate, to agree on a correct, comprehensive and comprehensible definition/description of the RS flip-flop. It could for example look like, as shown in the characteristic table.
Unlike all previous considerations with the following new interpretation for
Race Condition:
Caution, this state can not be saved! When S=R=0 follows then occurs a short-time instability and it is not sure in which stable state the RS flip flop ultimately tilts.
So simple could look a correct solution.

But it is not so simple.

The representatives of the doctrine are not so easy to convince. This can be understood. Only, up to now they are not to convince that S = R = 1 can be useful - neither through a clear description of the facts nor by the practical evidence.

The following experiences I made until now (April 2010):

• If the arguments are no longer sufficient, the discussion is simply (wordlessly) aborted. Maybe it's sometimes because the accuracy of my statements is detected (this also applies to the following circuits). But that is probably hard to admit.
• The discussion is essentially based on the repetition of the notion that the doctrine was correct.
• It is not trying to lead a discussion

However, I sometimes had the impression that my article was not read completely. Perhaps because he was not understood (deliberately?)

But:
A false statement does not become true by being merely repeated stereotyped.
Criterion is still the practice.

The representations on the sites Ideal pulse circuit and New JK flip-flop / JK latch show the rightness of the statements made here.